1. Field of the Invention
The present invention relates to a technical field of data processing and, more particularly, to a device and method for writing data in a processor to memory at unaligned location.
2. Description of Related Art
While a processor performs data processing, data alignment may affect the performances of many key operations, such as the operations of string, array and the like. As shown in FIG. 1, data to be processed, such as letters ‘ABCDEFGHIJKL’, normally exceeds the boundary or boundaries when writing it from registers R16, R17 and R18 to a memory 100 at addresses 101h to 10Ch. As such, since the memory 100 cannot process data, a processor must execute many additional operations before the data is stored in the memory 100 at unaligned location.
Upon this problem, a typical scheme is that after the data is loaded from the memory 100 at the unaligned location to the processor, various instructions in the processor are applied for obtaining required data. As shown in FIG. 2, for writing a data ‘ABCD’ to the unaligned location in the memory 100, data ‘abcd’ at address 100h is loaded to register R1 firstly to shift right 24 bits for saving required data ‘a’, and then shift left 24 bits for placing the data ‘a’ in position. Next, data ‘ABCD’ in register R16 is shifted right by eight bits and then stored in register R2 (0ABC). Next, an OR operation is applied to registers R1 and R2 to obtain a result to be stored in register R1 (aABC). Next, data ‘efgh’ at address 104h is loaded to register R1 firstly to shift left eight bits for saving required data ‘fgh’, and then shift right eight bits for placing the required data ‘fgh’ in suitable position. Next, data ABCD in register R16 is shifted left by 24 bits and then stored in register R2 (D000). Next, an OR operation is applied to registers R1 and R2 to obtain a result to be stored in register R1 (Dfgh). Finally, the content (Dfgh) of register R1 is written into the memory 100 at address 104h.
As cited, if a required length of unaligned data to be stored is n words (each having 32 bits), the typical scheme requires 12n instructions to describe the store operation and at least 12n instruction cycles to complete the store operation, which needs large memory space for storing required program codes and also increase processor load so as to result in poor performance.
Upon this problem, U.S. Pat. No. 4,814,976 granted to Hansen, et al. for a “RISC computer with unaligned reference handling and method for the same” performs the alignment as loading unaligned data and stores a data exceeding the boundary completely by two times. As shown in FIG. 3, data ABC in register R16 is written to memory addresses 101h to 103h. In this case, data at memory address 100h is unchanged. Next, data D in register 16 is written to memory address 104h. In this case, data in memory addresses 105h to 107h is unchanged. Similarly, contents of registers R17 and R18 are written sequentially to memory addresses 105h to 10Ch respectively.
As cited, if a required length of unaligned data to be loaded is n words, it needs 2n instructions to describe store operation and at least 2n instruction cycles to complete the store operation. Since read and write are repeated at the same memory position and register, the processor pipeline stall can be increased and the bus bandwidth is wasted. Especially to some systems without cache, delay can be obvious.
Therefore, it is desirable to provide an improved device and method for loading unaligned data to mitigate and/or obviate the aforementioned problems.